超大规模集成电路CADII-设计

A modern VLSI chip is a remarkably complex beast:  billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks).  How do people manage to design these complicated chips?  Answer:  a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design.  Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing.

Recommended Background:

Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms).  An understanding of basic digital design:  Boolean algebra, Kmaps, gates and flip flops, finite state machine design.  Linear algebra and calculus at the level of a junior or senior in engineering.  Elementary knowledge of RC linear circuits (at the level of an introductory physics class).

人们如何设计这些复杂的芯片？答：一系列计算机辅助设计（CAD）工具对芯片进行抽象描述，并逐步细化到最终设计。本课程主要介绍在建立特定应用集成电路（ASIC）或系统芯片（SoC）设计时所使用的主要设计工具。

• 课时1：Welcome and Introduction (19分17秒)

• 课时2：Two Tools Tutorial (4分2秒)

• 课时3：Basics (17分29秒)

• 课时4：Wirelength Estimation (15分5秒)

• 课时5：Simple Iterative Improvement Placement (12分18秒)

• 课时6：Iterative Improvement with Hill Climbing (15分16秒)

• 课时7：Simulated Annealing Placement (27分3秒)

• 课时8：Analytical Placement_ Quadratic Wirelength Model (14分39秒)

• 课时9：Analytical Placement_ Quadratic Placement (26分40秒)

• 课时10：Analytical Placement_ Recursive Partitioning (18分15秒)

• 课时11：Analytical Placement_ Recursive Partitioning Example (16分28秒)

• 课时12：Technology Mapping Basics (19分13秒)

• 课时13：Technology Mapping as Tree Covering (29分36秒)

• 课时14：Technology Mapping—Tree-ifying the Netlist (13分46秒)

• 课时15：Technology Mapping—Recursive Matching (9分0秒)

• 课时16：Technology Mapping—Minimum Cost Covering (16分8秒)

• 课时17：Technology Mapping—Detailed Covering Example (14分28秒)

• 课时18：Routing Basics (17分13秒)

• 课时19：Maze Routing_ 2-Point Nets in 1 Layer (16分35秒)

• 课时20：Maze Routing_ Multi-Point Nets (12分24秒)

• 课时21：Maze Routing_ Multi-Layer Routin (12分21秒)

• 课时22：Maze Routing_ Non-Uniform Grid Costs (14分57秒)

• 课时23：Implementation Mechanics_ How Expansion Works (23分32秒)

• 课时24：Implementation Mechanics_ Data Structures & Constraints (18分2秒)

• 课时25：Implementation Mechanics_ Depth First Search (14分6秒)

• 课时26：From Detailed Routing to Global Routing (15分48秒)

• 课时27：Basics (7分13秒)

• 课时28：Logic-Level Timing_ Basic Assumptions & Models (30分59秒)

• 课时29：Logic-Level Timing_ STA Delay Graph, ATs, RATs, and Slacks (27分30秒)

• 课时30：Logic-Level Timing_ A Detailed Example and the Role of Slack (10分2秒)

• 课时31：Logic-Level Timing_ Computing ATs, RATs, Slacks, and Worst Paths (26分55秒)

• 课时32：Interconnect Timing_ Electrical Models of Wire Delay (16分6秒)

• 课时33：Interconnect Timing_ The Elmore Delay Model (14分19秒)

• 课时34：Interconnect Timing_ Elmore Delay Examples (14分56秒)