system verilog视频教程

system verilog视频教程

• 课时1：SystemVerilog 01 DUT (41分0秒)

• 课时2：SystemVerilog 02 Testbench (51分21秒)

• 课时3：SystemVerilog 03 Language Basic one (1小时12分1秒)

• 课时4：SystemVerilog 04 Language Basic two (20分41秒)

• 课时5：SystemVerilog 05 Stimulus driven and received (23分53秒)

• 课时6：SystemVerilog 06 Concurrency (1小时4分24秒)

• 课时7：SystemVerilog 07 OOP-Encapsulation (1小时5分23秒)

• 课时8：SystemVerilog 08 Virtual Interface (11分23秒)

• 课时9：SystemVerilog 09 OOP-Randomization (56分11秒)

• 课时10：SystemVerilog 10 OOP-Inheritance (19分58秒)

• 课时11：SystemVerilog 11 Inter-Thread Communication (27分33秒)

• 课时12：SystemVerilog 12 Functional Coverage (33分6秒)

• 课时13：SystemVerilog 13 VMM Preview (16分54秒)