您的位置：EEWORLD大学堂 / 设计工具/EDA / 超大规模集成电路CADII-设计 / Logic-Level Timing_ Computing ATs, RATs, Slacks, and Worst Paths

A modern VLSI chip is a remarkably complex beast:  billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks).  How do people manage to design these complicated chips?  Answer:  a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design.  Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing.

Recommended Background:

Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms).  An understanding of basic digital design:  Boolean algebra, Kmaps, gates and flip flops, finite state machine design.  Linear algebra and calculus at the level of a junior or senior in engineering.  Elementary knowledge of RC linear circuits (at the level of an introductory physics class).

人们如何设计这些复杂的芯片？答：一系列计算机辅助设计（CAD）工具对芯片进行抽象描述，并逐步细化到最终设计。本课程主要介绍在建立特定应用集成电路（ASIC）或系统芯片（SoC）设计时所使用的主要设计工具。