• 本课程为精品课,您可以登录eeworld继续观看:
  • Multilevel Logic_ Algebraic Division
  • 登录
课程介绍
相关标签: 集成电路
A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc.  How do we design these complex chips?  Answer: CAD software tools.  Learn how to build thesA modern VLSI chip is a remarkably complex beast:  billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks).  How do people manage to design these complicated chips?  Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this first part of the course is on key Boolean logic representations that make it possible to synthesize, and to verify, the gate-level logic in these designs.  This is the first step of the design chain, as we move from logic to layout.    Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: Computational Boolean algebra, logic verification, and logic synthesis (2-level and multi-level).

Recommended Background

Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms).  An understanding of basic digital design:  Boolean algebra, Kmaps, gates and flip flops, finite state machine design.  Linear algebra and calculus at the level of a junior or senior in engineering.  Exposure to basic VLSI at an undergraduate level is nice -- but it’s not necessary.  We will keep the course self-contained, but students with some VLSI will be able to skip some background material.e tools in this class.

人们如何设计这些复杂的芯片?答:一系列计算机辅助设计(CAD)工具对芯片进行抽象描述,并逐步细化到最终设计。本课程主要介绍在建立特定应用集成电路(ASIC)或系统芯片(SoC)设计时所使用的主要设计工具。

显示全部 ↓
推荐视频

    猜您喜欢

    推荐帖子

    一个奇怪的编译问题
    在我电脑的E盘下建立了一个共享目录project,里面有多个子目录,存放了多个工程,我把不同的工程映射到不同的盘符,比如A工程映射到X盘,B工程映射到Y盘。编译的时候一般进入映射的盘符,比如X盘去编译,各个工程之前都编译很顺利,但是后来出现两个工程编译不过去,提示:final link failed:Invalid argument。叫同事映射我的工程到他电脑上X盘编译,警告变成了final li
    huahuikai 嵌入式系统
    关于应用程序与驱动程序如何动态传递数据?
    定义:#define IO_OPEN_COMCTL_CODE(FILE_DEVICE_COMSPY,0x080A,METHOD_BUFFERED, \FILE_ANY_ACCESS)想用下面传递串口号"\\??\\COM1"DeviceIoControl(m_hDevice,IO_OPEN_COM,sz1,12,NULL,0,&dwReturn,NULL);也就是说如何让sz1="\\??\\CO
    fewcome 嵌入式系统
    verilog语法错误请指正!
    `timescale 100ps/100psmodule buffer_blocking (out, in);input in;output out;parameter DELAY1 = 103;parameter DELAY2 = 103;always @(in)#DELAY1 out = #DELAY2 in;//这个地方报错,(vlog-2110) Illegal reference to
    eeleader FPGA/CPLD
    版主 没动静了?
    版主咋么没动静了,对这产品很关注啊!
    superdianzifans DIY/开源硬件专区
    MSP430 ADC12
    Curr_Volt = caltmp >> 12;//Curr_Volt = caltmp / 2^n[b]ptr[0] = Curr_Volt / 100;//Hex->Dec变换t1 = Curr_Volt - (ptr[0] * 100);ptr[2] = t1 / 10;ptr[3] = t1 - (ptr[2] * 10);ptr[1] = 10;//shuzi表中第10位对应符号"."
    zhoupinhua 微控制器 MCU
    【FPGA设计问题】关于时序与组合逻辑
    module reg4(clk,rstn,d,q);input[3:0] d;inputclk;inputrstn;output[3:0] q;reg[3:0] q;always @(rstn or clk)q=(~rstn)?0:d; endmodule组合与时序应该是数字领域一个最基本的问题,,但今天却迷糊了,,,突然分不清这二者了。。。还望指点迷津这个电平触发应该是组合逻辑了,那时序与组合到
    eeleader FPGA/CPLD

    推荐内容

    可能感兴趣器件

    完成课时学习+分/次

     
    EEWorld订阅号

     
    EEWorld服务号

     
    汽车开发圈

     
    机器人开发圈

    About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版 版权声明

    站点相关: 汽车电子 智能硬件

    北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

    电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2025 EEWORLD.com.cn, Inc. All rights reserved